Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
367996 |
1 |
|
|
T1 |
4530 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
331490 |
1 |
|
|
T2 |
4528 |
|
T3 |
778 |
|
T13 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175282 |
1 |
|
|
T1 |
1202 |
|
T2 |
1164 |
|
T3 |
212 |
lower_val |
173395 |
1 |
|
|
T1 |
1156 |
|
T2 |
1090 |
|
T3 |
190 |
zero_val |
1860 |
1 |
|
|
T1 |
5 |
|
T2 |
7 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
350318 |
1 |
|
|
T1 |
2228 |
|
T2 |
2148 |
|
T3 |
372 |
lower_val |
349162 |
1 |
|
|
T1 |
2302 |
|
T2 |
2382 |
|
T3 |
408 |
zero_val |
6 |
1 |
|
|
T151 |
2 |
|
T152 |
2 |
|
T153 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46314 |
1 |
|
|
T1 |
590 |
|
T12 |
9 |
|
T17 |
93 |
higher_val |
higher_val |
auto[1] |
41574 |
1 |
|
|
T2 |
584 |
|
T3 |
99 |
|
T13 |
77 |
higher_val |
lower_val |
auto[0] |
46057 |
1 |
|
|
T1 |
612 |
|
T3 |
1 |
|
T12 |
15 |
higher_val |
lower_val |
auto[1] |
41333 |
1 |
|
|
T2 |
580 |
|
T3 |
112 |
|
T13 |
77 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T151 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T152 |
2 |
|
T153 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
45809 |
1 |
|
|
T1 |
564 |
|
T2 |
1 |
|
T12 |
2 |
lower_val |
higher_val |
auto[1] |
40827 |
1 |
|
|
T2 |
487 |
|
T3 |
92 |
|
T13 |
81 |
lower_val |
lower_val |
auto[0] |
45645 |
1 |
|
|
T1 |
592 |
|
T12 |
12 |
|
T17 |
84 |
lower_val |
lower_val |
auto[1] |
41114 |
1 |
|
|
T2 |
602 |
|
T3 |
98 |
|
T13 |
80 |
zero_val |
higher_val |
auto[0] |
706 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
1 |
zero_val |
higher_val |
auto[1] |
207 |
1 |
|
|
T2 |
2 |
|
T13 |
2 |
|
T16 |
1 |
zero_val |
lower_val |
auto[0] |
693 |
1 |
|
|
T1 |
4 |
|
T3 |
1 |
|
T18 |
5 |
zero_val |
lower_val |
auto[1] |
254 |
1 |
|
|
T2 |
4 |
|
T15 |
2 |
|
T16 |
1 |