Group : kmac_env_pkg::kmac_env_cov::error_cg
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Group : kmac_env_pkg::kmac_env_cov::error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
89.66 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 21 3 18 85.71
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cmd 4 0 4 100.00 100 1 1 0
kmac_err_code 9 3 6 66.67 100 1 1 0
mode 3 0 3 100.00 100 1 1 0
strength 5 0 5 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_invalid_cmd_in_app_active 1 0 1 100.00 100 1 1 0
all_invalid_mode_strength_cfgs 7 0 7 100.00 100 1 1 0


Summary for Variable cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[CmdNone] 0 Excluded
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CmdStart] 693 1 T14 16 T24 11 T35 27
auto[CmdProcess] 95 1 T14 2 T24 4 T35 2
auto[CmdManualRun] 349 1 T14 9 T24 16 T35 8
auto[CmdDone] 1363 1 T14 37 T24 19 T35 53



Summary for Variable kmac_err_code

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 9 3 6 66.67


Automatically Generated Bins for kmac_err_code

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[ErrFatalError] 0 1 1
auto[ErrPackerIntegrity] 0 1 1
auto[ErrMsgFifoIntegrity] 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
auto[ErrNone] 0 Excluded
auto[ErrWaitTimerExpired] 0 Illegal
auto[ErrIncorrectEntropyMode] 0 Illegal
auto[ErrSwHashingWithoutEntropyReady] 0 Illegal
auto[ErrShadowRegUpdate] 0 Illegal
il 0 Illegal
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ErrKeyNotValid] 50 1 T21 1 T22 1 T23 1
auto[ErrSwPushedMsgFifo] 47 1 T35 1 T50 1 T36 3
auto[ErrSwIssuedCmdInAppActive] 32 1 T24 1 T35 3 T36 1
auto[ErrUnexpectedModeStrength] 593 1 T14 16 T24 9 T35 21
auto[ErrIncorrectFunctionName] 562 1 T14 14 T24 10 T35 23
auto[ErrSwCmdSequence] 1280 1 T14 37 T24 33 T35 43



Summary for Variable mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[Sha3] 393 1 T14 15 T24 17 T35 7
auto[Shake] 439 1 T14 8 T24 5 T35 19
auto[CShake] 1682 1 T14 44 T24 31 T35 65



Summary for Variable strength

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for strength

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[L128] 893 1 T14 32 T24 27 T35 28
auto[L224] 238 1 T14 1 T35 19 T50 5
auto[L256] 820 1 T14 10 T24 23 T35 22
auto[L384] 288 1 T14 6 T24 2 T35 11
auto[L512] 325 1 T14 18 T24 1 T35 11



Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
invalid_cmds 32 1 T24 1 T35 3 T36 1



Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 7 0 7 100.00


User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sha3_128_cfgs 171 1 T14 7 T24 6 T35 2
shake_224_invalid_cfg 29 1 T35 1 T50 2 T85 1
shake_384_invalid_cfg 40 1 T14 2 T35 1 T97 1
shake_512_invalid_cfg 44 1 T35 2 T97 1 T36 1
cshake_224_invalid_cfg 91 1 T14 1 T35 6 T50 1
cshake_384_invalid_cfg 106 1 T24 2 T35 6 T97 5
cshake_512_invalid_cfg 112 1 T14 6 T24 1 T35 3

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