Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
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Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 10352 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 9040 1 T1 38 T2 38 T3 17
len_5001_7500 14495 1 T1 36 T2 36 T3 17
len_2501_5000 9249 1 T1 36 T2 36 T3 17
len_1025_2500 5378 1 T1 22 T2 22 T3 10
len_769_1024 6501 1 T1 4 T2 4 T3 2
len_513_768 6873 1 T1 4 T2 4 T3 2
len_257_512 21656 1 T1 52 T2 52 T3 2
len_0_256 258829 1 T1 2017 T2 2017 T3 290
len_keccak_block_sizes[72] 726 1 T1 3 T2 3 T3 2
len_keccak_block_sizes[104] 627 1 T1 3 T2 3 T3 2
len_keccak_block_sizes[136] 519 1 T1 3 T2 3 T3 2
len_keccak_block_sizes[144] 428 1 T1 3 T2 3 T3 2
len_keccak_block_sizes[168] 326 1 T1 3 T2 3 T12 1
len_1 751 1 T1 3 T2 3 T3 2
len_0 1237 1 T1 3 T2 3 T3 2

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