Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101384659	1			T1	458744		T2	463310		T3	224307
all_pins[1]	101384659	1			T1	458744		T2	463310		T3	224307
all_pins[2]	101384659	1			T1	458744		T2	463310		T3	224307

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	303258463	1			T1	137287		T2	138650		T3	672326
values[0x1]	895514	1			T1	3358		T2	3422		T3	595
transitions[0x0=>0x1]	893187	1			T1	3358		T2	3422		T3	595
transitions[0x1=>0x0]	893208	1			T1	3358		T2	3422		T3	595

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100873423	1			T1	455386		T2	459888		T3	223712
all_pins[0]	values[0x1]	511236	1			T1	3358		T2	3422		T3	595
all_pins[0]	transitions[0x0=>0x1]	511221	1			T1	3358		T2	3422		T3	595
all_pins[0]	transitions[0x1=>0x0]	66	1			T49	4		T160	6		T161	3
all_pins[1]	values[0x0]	101384578	1			T1	458744		T2	463310		T3	224307
all_pins[1]	values[0x1]	81	1			T49	4		T160	6		T161	3
all_pins[1]	transitions[0x0=>0x1]	61	1			T49	4		T160	6		T161	3
all_pins[1]	transitions[0x1=>0x0]	384177	1			T14	1519		T24	538		T35	1290
all_pins[2]	values[0x0]	101000462	1			T1	458744		T2	463310		T3	224307
all_pins[2]	values[0x1]	384197	1			T14	1519		T24	538		T35	1290
all_pins[2]	transitions[0x0=>0x1]	381905	1			T14	1518		T24	538		T35	1290
all_pins[2]	transitions[0x1=>0x0]	508965	1			T1	3358		T2	3422		T3	595