Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	684	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5774	1			T12	1		T14	15		T18	59
len_601_800	12974	1			T12	11		T14	34		T18	156
len_401_600	8510	1			T12	4		T14	20		T18	77
len_201_400	16667	1			T1	251		T2	251		T12	3
len_65_200	74072	1			T1	680		T2	680		T12	2
len_min_for_xof_require_squeeze	1001	1			T1	10		T2	10		T12	1
len_keccak_block_sizes[72]	755	1			T1	5		T2	5		T18	1
len_keccak_block_sizes[104]	755	1			T1	5		T2	5		T180	9
len_keccak_block_sizes[136]	770	1			T1	5		T2	5		T42	3
len_keccak_block_sizes[144]	292	1			T1	5		T2	5		T18	1
len_keccak_block_sizes[168]	281	1			T1	5		T2	5		T42	1
len_datapath_width	14211	1			T1	5		T2	5		T18	16
len_2_63	215561	1			T1	1329		T2	1329		T3	390
len_1	58	1			T18	2		T42	1		T181	1