Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100305612	1			T1	277		T2	363		T3	3822
all_values[1]	100305612	1			T1	277		T2	363		T3	3822
all_values[2]	100305612	1			T1	277		T2	363		T3	3822

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

576965

1

T2

11

T3

326

T13

10

auto[1]

300339871

1

T1

831

T2

1078

T3

11140

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299385009

1

T1

798

T2

948

T3

11370

auto[1]

1531827

1

T1

33

T2

141

T3

96

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	200932	1			T2	9		T3	161		T16	118
all_values[0]	auto[0]	auto[1]	1959	1			T2	2		T3	2		T16	2
all_values[0]	auto[1]	auto[0]	99594071	1			T1	266		T2	307		T3	3629
all_values[0]	auto[1]	auto[1]	508650	1			T1	11		T2	45		T3	30
all_values[1]	auto[0]	auto[0]	158396	1			T13	4		T19	31		T38	2
all_values[1]	auto[0]	auto[1]	1577	1			T13	3		T19	2		T38	1
all_values[1]	auto[1]	auto[0]	99636607	1			T1	266		T2	316		T3	3790
all_values[1]	auto[1]	auto[1]	509032	1			T1	11		T2	47		T3	32
all_values[2]	auto[0]	auto[0]	212406	1			T3	161		T13	2		T14	11
all_values[2]	auto[0]	auto[1]	1695	1			T3	2		T13	1		T14	1
all_values[2]	auto[1]	auto[0]	99582597	1			T1	266		T2	316		T3	3629
all_values[2]	auto[1]	auto[1]	508914	1			T1	11		T2	47		T3	30