Group : kmac_env_pkg::config_unmasked_cg
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Group : kmac_env_pkg::config_unmasked_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::config_unmasked_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 23 0 23 100.00
Crosses 4 0 4 100.00


Variables for Group kmac_env_pkg::config_unmasked_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
key_len 5 0 5 100.00 100 1 1 0
kmac_en 2 0 2 100.00 100 1 1 2
mode 3 0 3 100.00 100 1 1 0
msg_endian 2 0 2 100.00 100 1 1 2
sideload 2 0 2 100.00 100 1 1 2
state_endian 2 0 2 100.00 100 1 1 2
strength 5 0 5 100.00 100 1 1 0
xof_en 2 0 2 100.00 100 1 1 2


Crosses for Group kmac_env_pkg::config_unmasked_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
kmac_cross 1 0 1 100.00 100 1 1 0
cshake_cross 1 0 1 100.00 100 1 1 0
shake_cross 1 0 1 100.00 100 1 1 0
sha3_cross 1 0 1 100.00 100 1 1 0


Summary for Variable key_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for key_len

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[Key128] 66371 1 T2 2 T13 74 T14 33
auto[Key192] 65809 1 T2 4 T13 84 T14 42
auto[Key256] 81958 1 T1 9 T2 6 T3 23
auto[Key384] 66249 1 T2 10 T13 74 T14 41
auto[Key512] 65879 1 T2 10 T13 82 T14 36



Summary for Variable kmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312515 1 T2 8 T3 2 T13 390
auto[1] 33751 1 T1 9 T2 24 T3 21



Summary for Variable mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[Sha3] 67389 1 T2 3 T13 390 T14 4
auto[Shake] 241876 1 T2 5 T3 2 T14 47
auto[CShake] 37001 1 T1 9 T2 24 T3 21



Summary for Variable msg_endian

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for msg_endian

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 172617 1 T1 2 T2 18 T3 10
auto[1] 173649 1 T1 7 T2 14 T3 13



Summary for Variable sideload

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sideload

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 336004 1 T1 9 T2 32 T13 390
auto[1] 10262 1 T3 23 T16 9 T17 90



Summary for Variable state_endian

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for state_endian

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 172932 1 T1 3 T2 16 T3 14
auto[1] 173334 1 T1 6 T2 16 T3 9



Summary for Variable strength

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for strength

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[L128] 139587 1 T1 6 T2 16 T3 9
auto[L224] 19848 1 T2 1 T13 390 T17 1
auto[L256] 158326 1 T1 3 T2 13 T3 14
auto[L384] 15836 1 T36 1 T38 310 T25 1
auto[L512] 12669 1 T2 2 T14 3 T19 1



Summary for Variable xof_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for xof_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 327062 1 T2 21 T3 9 T13 390
auto[1] 19204 1 T1 9 T2 11 T3 14



Summary for Cross kmac_cross

Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for kmac_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid_mode 0 Excluded
invalid_strength 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 33751 1 T1 9 T2 24 T3 21



Summary for Cross cshake_cross

Samples crossed: mode strength msg_endian state_endian
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for cshake_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid_mode 0 Excluded
invalid_strength 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 37001 1 T1 9 T2 24 T3 21



Summary for Cross shake_cross

Samples crossed: mode strength msg_endian state_endian
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for shake_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid_mode 0 Excluded
invalid_strength 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 241876 1 T2 5 T3 2 T14 47



Summary for Cross sha3_cross

Samples crossed: mode strength msg_endian state_endian
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for sha3_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid_mode 0 Excluded
invalid_strength 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 67389 1 T2 3 T13 390 T14 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%