Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
311534 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
383244 |
1 |
|
|
T1 |
16 |
|
T2 |
62 |
|
T3 |
44 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174188 |
1 |
|
|
T1 |
2 |
|
T2 |
10 |
|
T3 |
14 |
lower_val |
171291 |
1 |
|
|
T1 |
7 |
|
T2 |
12 |
|
T3 |
13 |
zero_val |
1830 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348060 |
1 |
|
|
T1 |
8 |
|
T2 |
42 |
|
T3 |
30 |
lower_val |
346714 |
1 |
|
|
T1 |
10 |
|
T2 |
22 |
|
T3 |
16 |
zero_val |
4 |
1 |
|
|
T157 |
2 |
|
T158 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
38722 |
1 |
|
|
T14 |
1 |
|
T15 |
3 |
|
T16 |
13 |
higher_val |
higher_val |
auto[1] |
48788 |
1 |
|
|
T1 |
2 |
|
T2 |
6 |
|
T3 |
10 |
higher_val |
lower_val |
auto[0] |
38712 |
1 |
|
|
T15 |
7 |
|
T16 |
15 |
|
T18 |
6 |
higher_val |
lower_val |
auto[1] |
47965 |
1 |
|
|
T2 |
4 |
|
T3 |
4 |
|
T13 |
98 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T157 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
38259 |
1 |
|
|
T3 |
1 |
|
T15 |
4 |
|
T16 |
8 |
lower_val |
higher_val |
auto[1] |
47570 |
1 |
|
|
T1 |
3 |
|
T2 |
7 |
|
T3 |
8 |
lower_val |
lower_val |
auto[0] |
38464 |
1 |
|
|
T16 |
10 |
|
T18 |
1 |
|
T19 |
4 |
lower_val |
lower_val |
auto[1] |
46998 |
1 |
|
|
T1 |
4 |
|
T2 |
5 |
|
T3 |
4 |
zero_val |
higher_val |
auto[0] |
666 |
1 |
|
|
T3 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
266 |
1 |
|
|
T19 |
1 |
|
T73 |
3 |
|
T74 |
1 |
zero_val |
lower_val |
auto[0] |
636 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
zero_val |
lower_val |
auto[1] |
262 |
1 |
|
|
T19 |
2 |
|
T73 |
1 |
|
T74 |
1 |