Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100305612	1			T1	277		T2	363		T3	3822
all_pins[1]	100305612	1			T1	277		T2	363		T3	3822
all_pins[2]	100305612	1			T1	277		T2	363		T3	3822

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300068660	1			T1	820		T2	1044		T3	11436
values[0x1]	848176	1			T1	11		T2	45		T3	30
transitions[0x0=>0x1]	846060	1			T1	11		T2	45		T3	30
transitions[0x1=>0x0]	846085	1			T1	11		T2	45		T3	30

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99796962	1			T1	266		T2	318		T3	3792
all_pins[0]	values[0x1]	508650	1			T1	11		T2	45		T3	30
all_pins[0]	transitions[0x0=>0x1]	508640	1			T1	11		T2	45		T3	30
all_pins[0]	transitions[0x1=>0x0]	61	1			T44	2		T171	2		T172	2
all_pins[1]	values[0x0]	100305541	1			T1	277		T2	363		T3	3822
all_pins[1]	values[0x1]	71	1			T44	2		T171	2		T172	2
all_pins[1]	transitions[0x0=>0x1]	64	1			T44	2		T171	2		T172	2
all_pins[1]	transitions[0x1=>0x0]	339448	1			T19	2376		T25	974		T50	6
all_pins[2]	values[0x0]	99966157	1			T1	277		T2	363		T3	3822
all_pins[2]	values[0x1]	339455	1			T19	2376		T25	974		T50	6
all_pins[2]	transitions[0x0=>0x1]	337356	1			T19	2358		T25	974		T50	6
all_pins[2]	transitions[0x1=>0x0]	506576	1			T1	11		T2	45		T3	30