Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100524244	1			T2	461651		T3	49539		T12	9601
all_values[1]	100524244	1			T2	461651		T3	49539		T12	9601
all_values[2]	100524244	1			T2	461651		T3	49539		T12	9601

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

569441

1

T2

11

T13

559

T14

3

auto[1]

301003291

1

T2

138494

T3

148617

T12

28803

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300043701

1

T2

137472

T3

148455

T12

28551

auto[1]

1529031

1

T2

10233

T3

162

T12

252

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	217984	1			T13	98		T14	1		T15	3101
all_values[0]	auto[0]	auto[1]	1959	1			T13	4		T14	2		T15	6
all_values[0]	auto[1]	auto[0]	99796583	1			T2	458240		T3	49485		T12	9517
all_values[0]	auto[1]	auto[1]	507718	1			T2	3411		T3	54		T12	84
all_values[1]	auto[0]	auto[0]	182322	1			T2	7		T13	428		T16	15
all_values[1]	auto[0]	auto[1]	1585	1			T2	4		T13	10		T16	3
all_values[1]	auto[1]	auto[0]	99832245	1			T2	458233		T3	49485		T12	9517
all_values[1]	auto[1]	auto[1]	508092	1			T2	3407		T3	54		T12	84
all_values[2]	auto[0]	auto[0]	164110	1			T13	16		T15	3101		T16	15
all_values[2]	auto[0]	auto[1]	1481	1			T13	3		T15	6		T16	3
all_values[2]	auto[1]	auto[0]	99850457	1			T2	458240		T3	49485		T12	9517
all_values[2]	auto[1]	auto[1]	508196	1			T2	3411		T3	54		T12	84