Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348368 |
1 |
|
|
T2 |
4530 |
|
T3 |
78 |
|
T12 |
2 |
auto[1] |
344876 |
1 |
|
|
T12 |
124 |
|
T13 |
164 |
|
T14 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173693 |
1 |
|
|
T2 |
1110 |
|
T3 |
18 |
|
T12 |
28 |
lower_val |
171502 |
1 |
|
|
T2 |
1050 |
|
T3 |
13 |
|
T12 |
20 |
zero_val |
1785 |
1 |
|
|
T2 |
13 |
|
T3 |
1 |
|
T12 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346284 |
1 |
|
|
T2 |
2296 |
|
T3 |
36 |
|
T12 |
68 |
lower_val |
346950 |
1 |
|
|
T2 |
2234 |
|
T3 |
42 |
|
T12 |
58 |
zero_val |
10 |
1 |
|
|
T135 |
2 |
|
T136 |
2 |
|
T137 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43282 |
1 |
|
|
T2 |
581 |
|
T3 |
7 |
|
T13 |
25 |
higher_val |
higher_val |
auto[1] |
43334 |
1 |
|
|
T12 |
13 |
|
T13 |
14 |
|
T14 |
58 |
higher_val |
lower_val |
auto[0] |
43526 |
1 |
|
|
T2 |
529 |
|
T3 |
11 |
|
T13 |
30 |
higher_val |
lower_val |
auto[1] |
43550 |
1 |
|
|
T12 |
15 |
|
T13 |
24 |
|
T14 |
60 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T138 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
43038 |
1 |
|
|
T2 |
520 |
|
T3 |
7 |
|
T13 |
16 |
lower_val |
higher_val |
auto[1] |
43001 |
1 |
|
|
T12 |
11 |
|
T13 |
21 |
|
T14 |
63 |
lower_val |
lower_val |
auto[0] |
42744 |
1 |
|
|
T2 |
530 |
|
T3 |
6 |
|
T13 |
16 |
lower_val |
lower_val |
auto[1] |
42718 |
1 |
|
|
T12 |
9 |
|
T13 |
16 |
|
T14 |
66 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T135 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
644 |
1 |
|
|
T2 |
8 |
|
T3 |
1 |
|
T12 |
1 |
zero_val |
higher_val |
auto[1] |
232 |
1 |
|
|
T13 |
1 |
|
T14 |
2 |
|
T24 |
5 |
zero_val |
lower_val |
auto[0] |
682 |
1 |
|
|
T2 |
5 |
|
T13 |
1 |
|
T17 |
1 |
zero_val |
lower_val |
auto[1] |
227 |
1 |
|
|
T13 |
1 |
|
T24 |
2 |
|
T25 |
1 |