Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100524244	1			T2	461651		T3	49539		T12	9601
all_pins[1]	100524244	1			T2	461651		T3	49539		T12	9601
all_pins[2]	100524244	1			T2	461651		T3	49539		T12	9601

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300777959	1			T2	138154		T3	148563		T12	28085
values[0x1]	794773	1			T2	3411		T3	54		T12	718
transitions[0x0=>0x1]	793045	1			T2	3411		T3	54		T12	718
transitions[0x1=>0x0]	793071	1			T2	3411		T3	54		T12	718

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100016526	1			T2	458240		T3	49485		T12	9517
all_pins[0]	values[0x1]	507718	1			T2	3411		T3	54		T12	84
all_pins[0]	transitions[0x0=>0x1]	507710	1			T2	3411		T3	54		T12	84
all_pins[0]	transitions[0x1=>0x0]	76	1			T40	5		T149	5		T150	4
all_pins[1]	values[0x0]	100524160	1			T2	461651		T3	49539		T12	9601
all_pins[1]	values[0x1]	84	1			T40	5		T149	5		T150	4
all_pins[1]	transitions[0x0=>0x1]	70	1			T40	5		T149	5		T150	4
all_pins[1]	transitions[0x1=>0x0]	286957	1			T12	634		T24	6690		T25	9900
all_pins[2]	values[0x0]	100237273	1			T2	461651		T3	49539		T12	8967
all_pins[2]	values[0x1]	286971	1			T12	634		T24	6690		T25	9900
all_pins[2]	transitions[0x0=>0x1]	285265	1			T12	634		T24	6654		T25	9831
all_pins[2]	transitions[0x1=>0x0]	506038	1			T2	3411		T3	54		T12	84