Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	656	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5677	1			T3	4		T12	7		T13	16
len_601_800	12303	1			T3	18		T12	15		T13	40
len_401_600	8202	1			T3	8		T12	10		T13	26
len_201_400	16418	1			T2	251		T3	6		T12	6
len_65_200	73841	1			T2	680		T3	2		T12	4
len_min_for_xof_require_squeeze	1009	1			T2	10		T16	1		T17	10
len_keccak_block_sizes[72]	760	1			T2	5		T3	1		T16	1
len_keccak_block_sizes[104]	754	1			T2	5		T16	1		T17	5
len_keccak_block_sizes[136]	762	1			T2	5		T16	2		T17	5
len_keccak_block_sizes[144]	290	1			T2	5		T17	5		T34	1
len_keccak_block_sizes[168]	279	1			T2	5		T17	5		T66	1
len_datapath_width	14032	1			T2	5		T13	5		T14	246
len_2_63	214306	1			T2	1329		T3	1		T12	2
len_1	47	1			T63	1		T30	1		T70	1