Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
10699790 | 
1 | 
 | 
 | 
T2 | 
47900 | 
 | 
T3 | 
6427 | 
 | 
T12 | 
9215 | 
| auto[1] | 
25683734 | 
1 | 
 | 
 | 
T2 | 
141800 | 
 | 
T3 | 
9360 | 
 | 
T12 | 
14110 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
4 | 
0 | 
4 | 
100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 
36264429 | 
1 | 
 | 
 | 
T2 | 
188764 | 
 | 
T3 | 
15753 | 
 | 
T12 | 
23283 | 
| triple_byte_access | 
39771 | 
1 | 
 | 
 | 
T2 | 
310 | 
 | 
T3 | 
9 | 
 | 
T12 | 
12 | 
| halfword_access | 
39847 | 
1 | 
 | 
 | 
T2 | 
316 | 
 | 
T3 | 
14 | 
 | 
T12 | 
17 | 
| byte_access | 
39477 | 
1 | 
 | 
 | 
T2 | 
310 | 
 | 
T3 | 
11 | 
 | 
T12 | 
13 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
8 | 
3 | 
5 | 
62.50  | 
3 | 
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
[triple_byte_access , halfword_access , byte_access] | 
-- | 
-- | 
3 | 
 | 
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
word_access | 
10580695 | 
1 | 
 | 
 | 
T2 | 
46964 | 
 | 
T3 | 
6393 | 
 | 
T12 | 
9173 | 
| auto[0] | 
triple_byte_access | 
39771 | 
1 | 
 | 
 | 
T2 | 
310 | 
 | 
T3 | 
9 | 
 | 
T12 | 
12 | 
| auto[0] | 
halfword_access | 
39847 | 
1 | 
 | 
 | 
T2 | 
316 | 
 | 
T3 | 
14 | 
 | 
T12 | 
17 | 
| auto[0] | 
byte_access | 
39477 | 
1 | 
 | 
 | 
T2 | 
310 | 
 | 
T3 | 
11 | 
 | 
T12 | 
13 | 
| auto[1] | 
word_access | 
25683734 | 
1 | 
 | 
 | 
T2 | 
141800 | 
 | 
T3 | 
9360 | 
 | 
T12 | 
14110 |