Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101162664	1			T2	923		T11	19907		T12	269
all_values[1]	101162664	1			T2	923		T11	19907		T12	269
all_values[2]	101162664	1			T2	923		T11	19907		T12	269

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

468571

1

T11

272

T13

454

T14

20

auto[1]

303019421

1

T2

2769

T11

59449

T12

807

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301956429

1

T2

2538

T11

59169

T12

771

auto[1]

1531563

1

T2

231

T11

552

T12

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	154126	1			T13	225		T14	10		T15	2510
all_values[0]	auto[0]	auto[1]	1902	1			T13	2		T14	10		T15	6
all_values[0]	auto[1]	auto[0]	100498017	1			T2	846		T11	19723		T12	257
all_values[0]	auto[1]	auto[1]	508619	1			T2	77		T11	184		T12	12
all_values[1]	auto[0]	auto[0]	148840	1			T11	133		T13	225		T15	379
all_values[1]	auto[0]	auto[1]	1360	1			T11	3		T13	2		T15	8
all_values[1]	auto[1]	auto[0]	100503303	1			T2	846		T11	19590		T12	257
all_values[1]	auto[1]	auto[1]	509161	1			T2	77		T11	181		T12	12
all_values[2]	auto[0]	auto[0]	160782	1			T11	133		T15	499		T17	1
all_values[2]	auto[0]	auto[1]	1561	1			T11	3		T15	7		T17	2
all_values[2]	auto[1]	auto[0]	100491361	1			T2	846		T11	19590		T12	257
all_values[2]	auto[1]	auto[1]	508960	1			T2	77		T11	181		T12	12