Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
344992 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T4 |
2 |
auto[1] |
349766 |
1 |
|
|
T2 |
102 |
|
T11 |
244 |
|
T12 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172996 |
1 |
|
|
T2 |
16 |
|
T4 |
1 |
|
T11 |
64 |
lower_val |
173019 |
1 |
|
|
T2 |
15 |
|
T3 |
1 |
|
T11 |
64 |
zero_val |
1812 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347440 |
1 |
|
|
T2 |
42 |
|
T3 |
2 |
|
T11 |
122 |
lower_val |
347306 |
1 |
|
|
T2 |
62 |
|
T4 |
2 |
|
T11 |
124 |
zero_val |
12 |
1 |
|
|
T28 |
2 |
|
T154 |
2 |
|
T155 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42930 |
1 |
|
|
T13 |
2 |
|
T14 |
109 |
|
T15 |
21 |
higher_val |
higher_val |
auto[1] |
43525 |
1 |
|
|
T2 |
4 |
|
T11 |
31 |
|
T12 |
1 |
higher_val |
lower_val |
auto[0] |
43010 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T14 |
98 |
higher_val |
lower_val |
auto[1] |
43529 |
1 |
|
|
T2 |
12 |
|
T11 |
33 |
|
T12 |
1 |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T156 |
1 |
|
T157 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
43062 |
1 |
|
|
T3 |
1 |
|
T13 |
6 |
|
T14 |
97 |
lower_val |
higher_val |
auto[1] |
43469 |
1 |
|
|
T2 |
8 |
|
T11 |
32 |
|
T12 |
2 |
lower_val |
lower_val |
auto[0] |
42732 |
1 |
|
|
T11 |
1 |
|
T13 |
6 |
|
T14 |
85 |
lower_val |
lower_val |
auto[1] |
43753 |
1 |
|
|
T2 |
7 |
|
T11 |
31 |
|
T12 |
1 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T28 |
1 |
|
T158 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T156 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
673 |
1 |
|
|
T3 |
1 |
|
T12 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
225 |
1 |
|
|
T64 |
3 |
|
T24 |
1 |
|
T36 |
1 |
zero_val |
lower_val |
auto[0] |
692 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T11 |
1 |
zero_val |
lower_val |
auto[1] |
222 |
1 |
|
|
T64 |
1 |
|
T24 |
1 |
|
T159 |
2 |