Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	646	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5565	1			T2	5		T11	17		T13	3
len_601_800	12422	1			T2	16		T11	48		T13	2
len_401_600	8207	1			T2	16		T11	33		T13	2
len_201_400	16205	1			T2	8		T11	10		T13	2
len_65_200	73908	1			T2	4		T11	9		T15	9
len_min_for_xof_require_squeeze	1005	1			T86	10		T180	9		T110	1
len_keccak_block_sizes[72]	753	1			T86	5		T180	9		T36	1
len_keccak_block_sizes[104]	742	1			T86	5		T180	9		T36	1
len_keccak_block_sizes[136]	758	1			T86	5		T180	9		T182	2
len_keccak_block_sizes[144]	282	1			T19	1		T86	5		T70	1
len_keccak_block_sizes[168]	278	1			T86	5		T182	2		T183	5
len_datapath_width	14100	1			T12	3		T15	8		T89	3
len_2_63	215122	1			T2	2		T11	5		T12	6
len_1	44	1			T36	1		T182	1		T184	1