Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99289067	1			T1	1155		T3	19892		T13	86217
all_values[1]	99289067	1			T1	1155		T3	19892		T13	86217
all_values[2]	99289067	1			T1	1155		T3	19892		T13	86217

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417855

1

T3

418

T13

3985

T14

148

auto[1]

297449346

1

T1

3465

T3

59258

T13

254666

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296331363

1

T1

3111

T3

59037

T13

257961

auto[1]

1535838

1

T1

354

T3

639

T13

690

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	147698	1			T3	205		T13	2036		T14	144
all_values[0]	auto[0]	auto[1]	2015	1			T3	4		T13	12		T14	2
all_values[0]	auto[1]	auto[0]	98629423	1			T1	1037		T3	19474		T13	83951
all_values[0]	auto[1]	auto[1]	509931	1			T1	118		T3	209		T13	218
all_values[1]	auto[0]	auto[0]	136756	1			T13	1780		T15	32		T16	5
all_values[1]	auto[0]	auto[1]	1446	1			T13	4		T15	2		T16	1
all_values[1]	auto[1]	auto[0]	98640365	1			T1	1037		T3	19679		T13	84207
all_values[1]	auto[1]	auto[1]	510500	1			T1	118		T3	213		T13	226
all_values[2]	auto[0]	auto[0]	128376	1			T3	205		T13	148		T14	2
all_values[2]	auto[0]	auto[1]	1564	1			T3	4		T13	5		T15	2
all_values[2]	auto[1]	auto[0]	98648745	1			T1	1037		T3	19474		T13	85839
all_values[2]	auto[1]	auto[1]	510382	1			T1	118		T3	209		T13	225