Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
317606 |
1 |
|
|
T1 |
154 |
|
T3 |
2 |
|
T13 |
256 |
auto[1] |
378624 |
1 |
|
|
T3 |
292 |
|
T13 |
116 |
|
T14 |
290 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174260 |
1 |
|
|
T1 |
44 |
|
T3 |
62 |
|
T13 |
88 |
lower_val |
172541 |
1 |
|
|
T1 |
47 |
|
T3 |
75 |
|
T13 |
94 |
zero_val |
1840 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T13 |
4 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347900 |
1 |
|
|
T1 |
82 |
|
T3 |
152 |
|
T13 |
198 |
lower_val |
348316 |
1 |
|
|
T1 |
72 |
|
T3 |
142 |
|
T13 |
174 |
zero_val |
14 |
1 |
|
|
T144 |
2 |
|
T145 |
2 |
|
T146 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
39619 |
1 |
|
|
T1 |
22 |
|
T13 |
29 |
|
T15 |
60 |
higher_val |
higher_val |
auto[1] |
47283 |
1 |
|
|
T3 |
35 |
|
T13 |
15 |
|
T14 |
33 |
higher_val |
lower_val |
auto[0] |
39800 |
1 |
|
|
T1 |
22 |
|
T13 |
29 |
|
T15 |
39 |
higher_val |
lower_val |
auto[1] |
47554 |
1 |
|
|
T3 |
27 |
|
T13 |
15 |
|
T14 |
39 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T147 |
1 |
|
T148 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T149 |
2 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
39368 |
1 |
|
|
T1 |
27 |
|
T13 |
27 |
|
T15 |
36 |
lower_val |
higher_val |
auto[1] |
46951 |
1 |
|
|
T3 |
32 |
|
T13 |
20 |
|
T14 |
36 |
lower_val |
lower_val |
auto[0] |
39224 |
1 |
|
|
T1 |
20 |
|
T13 |
32 |
|
T14 |
1 |
lower_val |
lower_val |
auto[1] |
46995 |
1 |
|
|
T3 |
43 |
|
T13 |
15 |
|
T14 |
49 |
lower_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T145 |
1 |
|
T147 |
1 |
|
T150 |
1 |
zero_val |
higher_val |
auto[0] |
687 |
1 |
|
|
T3 |
1 |
|
T13 |
2 |
|
T15 |
1 |
zero_val |
higher_val |
auto[1] |
263 |
1 |
|
|
T13 |
1 |
|
T37 |
2 |
|
T62 |
1 |
zero_val |
lower_val |
auto[0] |
647 |
1 |
|
|
T1 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
243 |
1 |
|
|
T62 |
1 |
|
T98 |
3 |
|
T25 |
1 |