Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99289067	1			T1	1155		T3	19892		T13	86217
all_pins[1]	99289067	1			T1	1155		T3	19892		T13	86217
all_pins[2]	99289067	1			T1	1155		T3	19892		T13	86217

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297035067	1			T1	3347		T3	59467		T13	256489
values[0x1]	832134	1			T1	118		T3	209		T13	2162
transitions[0x0=>0x1]	830155	1			T1	118		T3	209		T13	2151
transitions[0x1=>0x0]	830181	1			T1	118		T3	209		T13	2151

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98779136	1			T1	1037		T3	19683		T13	85999
all_pins[0]	values[0x1]	509931	1			T1	118		T3	209		T13	218
all_pins[0]	transitions[0x0=>0x1]	509919	1			T1	118		T3	209		T13	218
all_pins[0]	transitions[0x1=>0x0]	71	1			T152	2		T165	5		T166	3
all_pins[1]	values[0x0]	99288984	1			T1	1155		T3	19892		T13	86217
all_pins[1]	values[0x1]	83	1			T152	2		T165	5		T166	3
all_pins[1]	transitions[0x0=>0x1]	67	1			T152	2		T165	5		T166	3
all_pins[1]	transitions[0x1=>0x0]	322104	1			T13	1944		T29	578		T30	1402
all_pins[2]	values[0x0]	98966947	1			T1	1155		T3	19892		T13	84273
all_pins[2]	values[0x1]	322120	1			T13	1944		T29	578		T30	1402
all_pins[2]	transitions[0x0=>0x1]	320169	1			T13	1933		T29	577		T30	1402
all_pins[2]	transitions[0x1=>0x0]	508006	1			T1	118		T3	209		T13	207