Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	634	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5504	1			T1	8		T3	19		T13	23
len_601_800	12668	1			T1	32		T3	43		T13	51
len_401_600	8481	1			T1	19		T3	38		T13	37
len_201_400	16566	1			T1	8		T3	26		T13	14
len_65_200	73979	1			T1	7		T3	8		T13	12
len_min_for_xof_require_squeeze	1008	1			T14	1		T98	9		T179	10
len_keccak_block_sizes[72]	770	1			T1	1		T98	9		T25	1
len_keccak_block_sizes[104]	745	1			T1	1		T17	1		T98	9
len_keccak_block_sizes[136]	751	1			T98	9		T179	5		T26	1
len_keccak_block_sizes[144]	284	1			T179	5		T118	5		T180	1
len_keccak_block_sizes[168]	290	1			T179	5		T118	5		T39	1
len_datapath_width	14105	1			T3	1		T13	3		T14	1
len_2_63	215061	1			T1	2		T3	7		T13	43
len_1	49	1			T181	1		T135	1		T73	2