Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10794396 |
1 |
|
|
T1 |
12304 |
|
T3 |
23335 |
|
T13 |
25128 |
auto[1] |
25838169 |
1 |
|
|
T1 |
17510 |
|
T3 |
33372 |
|
T13 |
37028 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36512672 |
1 |
|
|
T1 |
29764 |
|
T3 |
56600 |
|
T13 |
62054 |
triple_byte_access |
39911 |
1 |
|
|
T1 |
17 |
|
T3 |
37 |
|
T13 |
41 |
halfword_access |
40140 |
1 |
|
|
T1 |
11 |
|
T3 |
38 |
|
T13 |
38 |
byte_access |
39842 |
1 |
|
|
T1 |
22 |
|
T3 |
32 |
|
T13 |
23 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10674503 |
1 |
|
|
T1 |
12254 |
|
T3 |
23228 |
|
T13 |
25026 |
auto[0] |
triple_byte_access |
39911 |
1 |
|
|
T1 |
17 |
|
T3 |
37 |
|
T13 |
41 |
auto[0] |
halfword_access |
40140 |
1 |
|
|
T1 |
11 |
|
T3 |
38 |
|
T13 |
38 |
auto[0] |
byte_access |
39842 |
1 |
|
|
T1 |
22 |
|
T3 |
32 |
|
T13 |
23 |
auto[1] |
word_access |
25838169 |
1 |
|
|
T1 |
17510 |
|
T3 |
33372 |
|
T13 |
37028 |