Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 269 1 T105 4 T106 4 T107 7
all_values[1] 269 1 T105 4 T106 4 T107 7
all_values[2] 269 1 T105 4 T106 4 T107 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 408 1 T105 6 T106 6 T107 8
auto[1] 399 1 T105 6 T106 6 T107 13


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 368 1 T105 7 T106 8 T107 8
auto[1] 439 1 T105 5 T106 4 T107 13


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 471 1 T105 10 T106 9 T107 10
auto[1] 336 1 T105 2 T106 3 T107 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 48 1 T106 2 T158 1 T159 2
all_values[0] auto[0] auto[0] auto[1] 34 1 T105 1 T107 2 T160 1
all_values[0] auto[0] auto[1] auto[0] 49 1 T106 2 T107 1 T160 2
all_values[0] auto[0] auto[1] auto[1] 21 1 T105 2 T161 1 T162 1
all_values[0] auto[1] auto[0] auto[1] 72 1 T105 1 T107 3 T160 2
all_values[0] auto[1] auto[1] auto[1] 45 1 T107 1 T160 2 T141 2
all_values[1] auto[0] auto[0] auto[0] 70 1 T105 1 T106 1 T160 1
all_values[1] auto[0] auto[1] auto[0] 89 1 T105 3 T106 2 T107 4
all_values[1] auto[1] auto[0] auto[1] 47 1 T107 1 T160 1 T163 1
all_values[1] auto[1] auto[1] auto[1] 63 1 T106 1 T107 2 T160 3
all_values[2] auto[0] auto[0] auto[0] 59 1 T105 2 T107 2 T141 1
all_values[2] auto[0] auto[0] auto[1] 22 1 T106 1 T160 1 T141 1
all_values[2] auto[0] auto[1] auto[0] 53 1 T105 1 T106 1 T107 1
all_values[2] auto[0] auto[1] auto[1] 26 1 T164 1 T162 1 T159 1
all_values[2] auto[1] auto[0] auto[1] 56 1 T105 1 T106 2 T163 2
all_values[2] auto[1] auto[1] auto[1] 53 1 T107 4 T160 5 T141 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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