Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100044861	1			T2	559054		T4	277		T9	109774
all_values[1]	100044861	1			T2	559054		T4	277		T9	109774
all_values[2]	100044861	1			T2	559054		T4	277		T9	109774

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

499238

1

T2

3

T4

24

T9

3

auto[1]

299635345

1

T2

167715

T4

807

T9

329319

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298600302

1

T2

166665

T4

789

T9

328260

auto[1]

1534281

1

T2

10509

T4

42

T9

1062

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	151320	1			T4	8		T13	4		T16	1
all_values[0]	auto[0]	auto[1]	2103	1			T4	4		T13	2		T16	2
all_values[0]	auto[1]	auto[0]	99382114	1			T2	555551		T4	255		T9	109420
all_values[0]	auto[1]	auto[1]	509324	1			T2	3503		T4	10		T9	354
all_values[1]	auto[0]	auto[0]	170656	1			T9	2		T13	9		T14	347
all_values[1]	auto[0]	auto[1]	1707	1			T9	1		T13	3		T14	2
all_values[1]	auto[1]	auto[0]	99362778	1			T2	555551		T4	263		T9	109418
all_values[1]	auto[1]	auto[1]	509720	1			T2	3503		T4	14		T9	353
all_values[2]	auto[0]	auto[0]	171764	1			T2	2		T4	8		T14	347
all_values[2]	auto[0]	auto[1]	1688	1			T2	1		T4	4		T14	2
all_values[2]	auto[1]	auto[0]	99361670	1			T2	555549		T4	255		T9	109420
all_values[2]	auto[1]	auto[1]	509739	1			T2	3502		T4	10		T9	354