Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
373108 |
1 |
|
|
T1 |
2 |
|
T2 |
4674 |
|
T3 |
2 |
auto[1] |
322506 |
1 |
|
|
T4 |
16 |
|
T15 |
618 |
|
T18 |
212 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174282 |
1 |
|
|
T2 |
1116 |
|
T3 |
1 |
|
T4 |
3 |
lower_val |
171676 |
1 |
|
|
T2 |
1142 |
|
T4 |
6 |
|
T9 |
130 |
zero_val |
1861 |
1 |
|
|
T1 |
1 |
|
T2 |
7 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348336 |
1 |
|
|
T2 |
2262 |
|
T4 |
14 |
|
T9 |
226 |
lower_val |
347266 |
1 |
|
|
T1 |
2 |
|
T2 |
2412 |
|
T3 |
2 |
zero_val |
12 |
1 |
|
|
T139 |
2 |
|
T163 |
2 |
|
T164 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46871 |
1 |
|
|
T2 |
526 |
|
T9 |
56 |
|
T13 |
2 |
higher_val |
higher_val |
auto[1] |
40601 |
1 |
|
|
T4 |
2 |
|
T15 |
69 |
|
T18 |
39 |
higher_val |
lower_val |
auto[0] |
46288 |
1 |
|
|
T2 |
590 |
|
T3 |
1 |
|
T9 |
68 |
higher_val |
lower_val |
auto[1] |
40521 |
1 |
|
|
T4 |
1 |
|
T15 |
78 |
|
T18 |
29 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T165 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
46689 |
1 |
|
|
T2 |
551 |
|
T4 |
1 |
|
T9 |
56 |
lower_val |
higher_val |
auto[1] |
39801 |
1 |
|
|
T4 |
4 |
|
T15 |
95 |
|
T18 |
23 |
lower_val |
lower_val |
auto[0] |
45820 |
1 |
|
|
T2 |
591 |
|
T9 |
74 |
|
T13 |
4 |
lower_val |
lower_val |
auto[1] |
39361 |
1 |
|
|
T4 |
1 |
|
T15 |
65 |
|
T18 |
27 |
lower_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T139 |
2 |
|
T166 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T167 |
1 |
|
T165 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
711 |
1 |
|
|
T2 |
4 |
|
T4 |
1 |
|
T9 |
4 |
zero_val |
higher_val |
auto[1] |
239 |
1 |
|
|
T18 |
1 |
|
T42 |
1 |
|
T27 |
2 |
zero_val |
lower_val |
auto[0] |
671 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
240 |
1 |
|
|
T18 |
1 |
|
T128 |
3 |
|
T168 |
2 |