Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100044861	1			T2	559054		T4	277		T9	109774
all_pins[1]	100044861	1			T2	559054		T4	277		T9	109774
all_pins[2]	100044861	1			T2	559054		T4	277		T9	109774

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299273154	1			T2	167365		T4	821		T9	328968
values[0x1]	861429	1			T2	3503		T4	10		T9	354
transitions[0x0=>0x1]	859187	1			T2	3503		T4	10		T9	354
transitions[0x1=>0x0]	859208	1			T2	3503		T4	10		T9	354

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99535537	1			T2	555551		T4	267		T9	109420
all_pins[0]	values[0x1]	509324	1			T2	3503		T4	10		T9	354
all_pins[0]	transitions[0x0=>0x1]	509310	1			T2	3503		T4	10		T9	354
all_pins[0]	transitions[0x1=>0x0]	57	1			T178	3		T179	2		T180	4
all_pins[1]	values[0x0]	100044790	1			T2	559054		T4	277		T9	109774
all_pins[1]	values[0x1]	71	1			T178	3		T179	2		T180	4
all_pins[1]	transitions[0x0=>0x1]	59	1			T178	3		T179	2		T180	4
all_pins[1]	transitions[0x1=>0x0]	352022	1			T18	2583		T30	435		T31	631
all_pins[2]	values[0x0]	99692827	1			T2	559054		T4	277		T9	109774
all_pins[2]	values[0x1]	352034	1			T18	2583		T30	435		T31	631
all_pins[2]	transitions[0x0=>0x1]	349818	1			T18	2569		T30	435		T31	631
all_pins[2]	transitions[0x1=>0x0]	507129	1			T2	3503		T4	10		T9	354