Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100762552	1			T1	222052		T3	50707		T13	16843
all_values[1]	100762552	1			T1	222052		T3	50707		T13	16843
all_values[2]	100762552	1			T1	222052		T3	50707		T13	16843

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

530761

1

T1

19

T3

6262

T13

2

auto[1]

301756895

1

T1

666137

T3

145859

T13

50527

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300758889

1

T1

664383

T3

151914

T13

50022

auto[1]

1528767

1

T1

1773

T3

207

T13

507

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	188055	1			T1	3		T3	6254		T13	1
all_values[0]	auto[0]	auto[1]	2120	1			T1	4		T3	8		T14	4
all_values[0]	auto[1]	auto[0]	100064908	1			T1	221458		T3	44384		T13	16673
all_values[0]	auto[1]	auto[1]	507469	1			T1	587		T3	61		T13	169
all_values[1]	auto[0]	auto[0]	138833	1			T1	7		T13	1		T17	663
all_values[1]	auto[0]	auto[1]	1548	1			T1	5		T17	3		T18	1
all_values[1]	auto[1]	auto[0]	100114130	1			T1	221454		T3	50638		T13	16673
all_values[1]	auto[1]	auto[1]	508041	1			T1	586		T3	69		T13	169
all_values[2]	auto[0]	auto[0]	198603	1			T14	15		T15	2		T17	312
all_values[2]	auto[0]	auto[1]	1602	1			T14	4		T15	1		T17	6
all_values[2]	auto[1]	auto[0]	100054360	1			T1	221461		T3	50638		T13	16674
all_values[2]	auto[1]	auto[1]	507987	1			T1	591		T3	69		T13	169