Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100762552	1			T1	222052		T3	50707		T13	16843
all_pins[1]	100762552	1			T1	222052		T3	50707		T13	16843
all_pins[2]	100762552	1			T1	222052		T3	50707		T13	16843

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301504873	1			T1	665569		T3	152060		T13	50360
values[0x1]	782783	1			T1	587		T3	61		T13	169
transitions[0x0=>0x1]	781102	1			T1	587		T3	61		T13	169
transitions[0x1=>0x0]	781127	1			T1	587		T3	61		T13	169

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100255083	1			T1	221465		T3	50646		T13	16674
all_pins[0]	values[0x1]	507469	1			T1	587		T3	61		T13	169
all_pins[0]	transitions[0x0=>0x1]	507456	1			T1	587		T3	61		T13	169
all_pins[0]	transitions[0x1=>0x0]	70	1			T42	3		T172	14		T173	2
all_pins[1]	values[0x0]	100762469	1			T1	222052		T3	50707		T13	16843
all_pins[1]	values[0x1]	83	1			T42	3		T172	14		T173	2
all_pins[1]	transitions[0x0=>0x1]	70	1			T42	3		T172	14		T173	2
all_pins[1]	transitions[0x1=>0x0]	275218	1			T17	838		T23	728		T24	15145
all_pins[2]	values[0x0]	100487321	1			T1	222052		T3	50707		T13	16843
all_pins[2]	values[0x1]	275231	1			T17	838		T23	728		T24	15145
all_pins[2]	transitions[0x0=>0x1]	273576	1			T17	833		T23	728		T24	15052
all_pins[2]	transitions[0x1=>0x0]	505839	1			T1	587		T3	61		T13	169