Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	632	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5413	1			T3	8		T13	20		T14	5
len_601_800	12197	1			T3	19		T13	42		T14	11
len_401_600	8193	1			T3	8		T13	34		T14	2
len_201_400	16459	1			T3	4		T13	5		T14	3
len_65_200	73663	1			T3	1		T13	4		T14	1
len_min_for_xof_require_squeeze	1008	1			T86	1		T104	10		T106	10
len_keccak_block_sizes[72]	770	1			T104	5		T106	5		T108	5
len_keccak_block_sizes[104]	744	1			T104	5		T106	5		T108	5
len_keccak_block_sizes[136]	760	1			T13	1		T59	1		T104	5
len_keccak_block_sizes[144]	285	1			T23	1		T42	1		T104	5
len_keccak_block_sizes[168]	290	1			T59	1		T104	5		T106	5
len_datapath_width	14073	1			T13	1		T15	246		T17	10
len_2_63	214743	1			T1	390		T3	2		T13	55
len_1	62	1			T17	1		T86	1		T25	3