Group : kmac_env_pkg::kmac_env_cov::sideload_cg
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Group : kmac_env_pkg::kmac_env_cov::sideload_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::sideload_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::sideload_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
in_app_keymgr 2 0 2 100.00 100 1 1 2
kmac_mode 2 0 2 100.00 100 1 1 2
sideload 2 0 2 100.00 100 1 1 2


Crosses for Group kmac_env_pkg::kmac_env_cov::sideload_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sideload_cross 4 0 4 100.00 100 1 1 0


Summary for Variable in_app_keymgr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for in_app_keymgr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 340369 1 T1 382 T3 44 T13 189
auto[1] 3345 1 T13 27 T19 1 T23 1



Summary for Variable kmac_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306825 1 T1 382 T3 16 T13 103
auto[1] 36889 1 T3 28 T13 113 T14 16



Summary for Variable sideload

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sideload

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 329927 1 T1 382 T3 44 T13 154
auto[1] 13787 1 T13 62 T17 20 T19 1



Summary for Cross sideload_cross

Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 4 0 4 100.00


User Defined Cross Bins for sideload_cross

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_kmac_valid_sideload 13787 1 T13 62 T17 20 T19 1
sw_kmac_invalid_sideload 329927 1 T1 382 T3 44 T13 154
app_valid_sideload 13787 1 T13 62 T17 20 T19 1
app_invalid_sideload 329927 1 T1 382 T3 44 T13 154

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