Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101479454	1			T1	142516		T2	222554		T3	9
all_values[1]	101479454	1			T1	142516		T2	222554		T3	9
all_values[2]	101479454	1			T1	142516		T2	222554		T3	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

508332

1

T1

1405

T2

7

T3

9

auto[1]

303930030

1

T1

426143

T2

667655

T3

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302903958

1

T1

426183

T2

665871

T3

27

auto[1]

1534404

1

T1

1365

T2

1791

T4

588

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	148834	1			T1	573		T13	119		T14	3
all_values[0]	auto[0]	auto[1]	1946	1			T1	10		T13	4		T14	4
all_values[0]	auto[1]	auto[0]	100819152	1			T1	141488		T2	221957		T3	9
all_values[0]	auto[1]	auto[1]	509522	1			T1	445		T2	597		T4	196
all_values[1]	auto[0]	auto[0]	177272	1			T1	291		T3	9		T13	119
all_values[1]	auto[0]	auto[1]	1560	1			T1	1		T13	4		T14	2
all_values[1]	auto[1]	auto[0]	100790714	1			T1	141770		T2	221957		T4	17794
all_values[1]	auto[1]	auto[1]	509908	1			T1	454		T2	597		T4	196
all_values[2]	auto[0]	auto[0]	177250	1			T1	526		T2	4		T4	15
all_values[2]	auto[0]	auto[1]	1470	1			T1	4		T2	3		T4	1
all_values[2]	auto[1]	auto[0]	100790736	1			T1	141535		T2	221953		T3	9
all_values[2]	auto[1]	auto[1]	509998	1			T1	451		T2	594		T4	195