Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335644 |
1 |
|
|
T1 |
382 |
|
T2 |
780 |
|
T3 |
2 |
auto[1] |
360432 |
1 |
|
|
T1 |
324 |
|
T19 |
232 |
|
T89 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174546 |
1 |
|
|
T1 |
185 |
|
T2 |
193 |
|
T4 |
93 |
lower_val |
172129 |
1 |
|
|
T1 |
172 |
|
T2 |
202 |
|
T3 |
1 |
zero_val |
1988 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347758 |
1 |
|
|
T1 |
356 |
|
T2 |
400 |
|
T4 |
190 |
lower_val |
348304 |
1 |
|
|
T1 |
350 |
|
T2 |
380 |
|
T3 |
2 |
zero_val |
14 |
1 |
|
|
T171 |
2 |
|
T172 |
2 |
|
T173 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41664 |
1 |
|
|
T1 |
44 |
|
T2 |
93 |
|
T4 |
41 |
higher_val |
higher_val |
auto[1] |
45526 |
1 |
|
|
T1 |
43 |
|
T19 |
26 |
|
T89 |
593 |
higher_val |
lower_val |
auto[0] |
42228 |
1 |
|
|
T1 |
55 |
|
T2 |
100 |
|
T4 |
52 |
higher_val |
lower_val |
auto[1] |
45125 |
1 |
|
|
T1 |
43 |
|
T19 |
16 |
|
T89 |
595 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T174 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T172 |
1 |
|
T175 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
41198 |
1 |
|
|
T1 |
42 |
|
T2 |
103 |
|
T4 |
45 |
lower_val |
higher_val |
auto[1] |
44738 |
1 |
|
|
T1 |
48 |
|
T19 |
28 |
|
T89 |
579 |
lower_val |
lower_val |
auto[0] |
41643 |
1 |
|
|
T1 |
47 |
|
T2 |
99 |
|
T3 |
1 |
lower_val |
lower_val |
auto[1] |
44547 |
1 |
|
|
T1 |
35 |
|
T19 |
30 |
|
T89 |
569 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T171 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T173 |
1 |
|
T176 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
702 |
1 |
|
|
T1 |
2 |
|
T4 |
1 |
|
T14 |
5 |
zero_val |
higher_val |
auto[1] |
280 |
1 |
|
|
T1 |
2 |
|
T19 |
2 |
|
T89 |
2 |
zero_val |
lower_val |
auto[0] |
735 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
271 |
1 |
|
|
T1 |
1 |
|
T19 |
2 |
|
T69 |
5 |