Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg
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Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
hash_mode 3 0 3 100.00 100 1 1 0
kmac_mode 2 0 2 100.00 100 1 1 2
msgfifo_depth 11 0 11 100.00 100 1 1 0
msgfifo_empty 2 0 2 100.00 100 1 1 2
msgfifo_full 2 0 2 100.00 100 1 1 2


Summary for Variable hash_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for hash_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cshake 11964572 1 T1 115103 T4 10293 T13 9403
shake 55542358 1 T1 39102 T3 9 T4 8621
sha3 35425132 1 T1 2311 T2 221773 T4 267



Summary for Variable kmac_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 90966384 1 T1 41402 T2 221773 T3 9
auto[1] 11965678 1 T1 115114 T4 10313 T13 9403



Summary for Variable msgfifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for msgfifo_depth

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
depth[0x00] 101580311 1 T1 149892 T2 221773 T3 9
depth[0x01] 871285 1 T1 3997 T4 1 T13 334
depth[0x02] 156866 1 T1 923 T13 123 T6 2
depth[0x03] 127331 1 T1 756 T13 106 T6 3
depth[0x04] 80541 1 T1 468 T13 49 T6 2
depth[0x05] 48033 1 T1 217 T13 14 T19 13
depth[0x06] 18599 1 T1 63 T39 164 T29 327
depth[0x07] 451 1 T1 4 T29 3 T142 38
depth[0x08] 1534 1 T1 4 T39 15 T29 35
depth[0x09] 1441 1 T1 11 T39 4 T29 19
depth[0x0a] 45670 1 T1 181 T39 362 T29 764



Summary for Variable msgfifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for msgfifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1351751 1 T1 6624 T4 1 T13 626
auto[1] 101580311 1 T1 149892 T2 221773 T3 9



Summary for Variable msgfifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for msgfifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 102886392 1 T1 156335 T2 221773 T3 9
auto[1] 45670 1 T1 181 T39 362 T29 764

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%