Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101479454	1			T1	142516		T2	222554		T3	9
all_pins[1]	101479454	1			T1	142516		T2	222554		T3	9
all_pins[2]	101479454	1			T1	142516		T2	222554		T3	9

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	303573893	1			T1	424367		T2	667065		T3	27
values[0x1]	864469	1			T1	3181		T2	597		T4	196
transitions[0x0=>0x1]	862254	1			T1	3163		T2	597		T4	196
transitions[0x1=>0x0]	862276	1			T1	3163		T2	597		T4	196

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100969932	1			T1	142071		T2	221957		T3	9
all_pins[0]	values[0x1]	509522	1			T1	445		T2	597		T4	196
all_pins[0]	transitions[0x0=>0x1]	509511	1			T1	445		T2	597		T4	196
all_pins[0]	transitions[0x1=>0x0]	59	1			T42	3		T183	3		T184	2
all_pins[1]	values[0x0]	101479384	1			T1	142516		T2	222554		T3	9
all_pins[1]	values[0x1]	70	1			T42	3		T183	3		T184	2
all_pins[1]	transitions[0x0=>0x1]	58	1			T42	3		T183	3		T184	2
all_pins[1]	transitions[0x1=>0x0]	354865	1			T1	2736		T19	243		T43	1
all_pins[2]	values[0x0]	101124577	1			T1	139780		T2	222554		T3	9
all_pins[2]	values[0x1]	354877	1			T1	2736		T19	243		T43	1
all_pins[2]	transitions[0x0=>0x1]	352685	1			T1	2718		T19	243		T43	1
all_pins[2]	transitions[0x1=>0x0]	507352	1			T1	427		T2	597		T4	196