Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10778790 |
1 |
|
|
T1 |
44597 |
|
T2 |
2730 |
|
T4 |
24549 |
auto[1] |
25804652 |
1 |
|
|
T1 |
66512 |
|
T2 |
19500 |
|
T4 |
36680 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36463770 |
1 |
|
|
T1 |
110891 |
|
T2 |
22230 |
|
T4 |
61135 |
triple_byte_access |
39887 |
1 |
|
|
T1 |
77 |
|
T4 |
30 |
|
T13 |
18 |
halfword_access |
39927 |
1 |
|
|
T1 |
62 |
|
T4 |
33 |
|
T13 |
13 |
byte_access |
39858 |
1 |
|
|
T1 |
79 |
|
T4 |
31 |
|
T13 |
17 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10659118 |
1 |
|
|
T1 |
44379 |
|
T2 |
2730 |
|
T4 |
24455 |
auto[0] |
triple_byte_access |
39887 |
1 |
|
|
T1 |
77 |
|
T4 |
30 |
|
T13 |
18 |
auto[0] |
halfword_access |
39927 |
1 |
|
|
T1 |
62 |
|
T4 |
33 |
|
T13 |
13 |
auto[0] |
byte_access |
39858 |
1 |
|
|
T1 |
79 |
|
T4 |
31 |
|
T13 |
17 |
auto[1] |
word_access |
25804652 |
1 |
|
|
T1 |
66512 |
|
T2 |
19500 |
|
T4 |
36680 |