Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 269 1 T129 4 T130 4 T131 7
all_values[1] 269 1 T129 4 T130 4 T131 7
all_values[2] 269 1 T129 4 T130 4 T131 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 440 1 T129 8 T130 8 T131 12
auto[1] 367 1 T129 4 T130 4 T131 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 366 1 T129 5 T130 10 T131 7
auto[1] 441 1 T129 7 T130 2 T131 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 495 1 T129 8 T130 10 T131 10
auto[1] 312 1 T129 4 T130 2 T131 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 58 1 T130 4 T131 3 T177 1
all_values[0] auto[0] auto[0] auto[1] 27 1 T129 1 T131 2 T178 1
all_values[0] auto[0] auto[1] auto[0] 41 1 T129 2 T177 1 T179 1
all_values[0] auto[0] auto[1] auto[1] 41 1 T177 1 T178 1 T179 1
all_values[0] auto[1] auto[0] auto[1] 50 1 T131 1 T177 1 T180 1
all_values[0] auto[1] auto[1] auto[1] 52 1 T129 1 T131 1 T177 3
all_values[1] auto[0] auto[0] auto[0] 93 1 T129 1 T130 1 T131 1
all_values[1] auto[0] auto[1] auto[0] 65 1 T129 1 T130 1 T131 2
all_values[1] auto[1] auto[0] auto[1] 59 1 T129 2 T131 2 T177 2
all_values[1] auto[1] auto[1] auto[1] 52 1 T130 2 T131 2 T177 1
all_values[2] auto[0] auto[0] auto[0] 62 1 T129 1 T130 3 T131 1
all_values[2] auto[0] auto[0] auto[1] 30 1 T129 2 T181 1 T182 1
all_values[2] auto[0] auto[1] auto[0] 47 1 T130 1 T177 2 T181 2
all_values[2] auto[0] auto[1] auto[1] 31 1 T131 1 T178 3 T179 1
all_values[2] auto[1] auto[0] auto[1] 61 1 T129 1 T131 2 T177 1
all_values[2] auto[1] auto[1] auto[1] 38 1 T131 3 T177 1 T178 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%