Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100130787	1			T1	59634		T2	4		T3	221747
all_values[1]	100130787	1			T1	59634		T2	4		T3	221747
all_values[2]	100130787	1			T1	59634		T2	4		T3	221747

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

511805

1

T1

339

T2

8

T3

3

auto[1]

299880556

1

T1

178563

T2

4

T3

665238

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298864878

1

T1

178323

T2

12

T3

663462

auto[1]

1527483

1

T1

579

T3

1779

T4

69

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	188686	1			T1	192		T3	1		T4	135
all_values[0]	auto[0]	auto[1]	1885	1			T1	18		T3	2		T4	2
all_values[0]	auto[1]	auto[0]	99432940	1			T1	59249		T2	4		T3	221153
all_values[0]	auto[1]	auto[1]	507276	1			T1	175		T3	591		T4	21
all_values[1]	auto[0]	auto[0]	178023	1			T1	98		T2	4		T16	1
all_values[1]	auto[0]	auto[1]	1544	1			T1	10		T17	1		T38	2
all_values[1]	auto[1]	auto[0]	99443603	1			T1	59343		T3	221154		T4	2353
all_values[1]	auto[1]	auto[1]	507617	1			T1	183		T3	593		T4	23
all_values[2]	auto[0]	auto[0]	140161	1			T1	16		T2	4		T4	135
all_values[2]	auto[0]	auto[1]	1506	1			T1	5		T4	2		T14	3
all_values[2]	auto[1]	auto[0]	99481465	1			T1	59425		T3	221154		T4	2218
all_values[2]	auto[1]	auto[1]	507655	1			T1	188		T3	593		T4	21