Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
368984 |
1 |
|
|
T1 |
114 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
322446 |
1 |
|
|
T1 |
136 |
|
T3 |
778 |
|
T4 |
44 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172346 |
1 |
|
|
T1 |
82 |
|
T3 |
164 |
|
T4 |
2 |
lower_val |
171954 |
1 |
|
|
T1 |
75 |
|
T3 |
218 |
|
T4 |
13 |
zero_val |
1788 |
1 |
|
|
T1 |
4 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345170 |
1 |
|
|
T1 |
116 |
|
T3 |
386 |
|
T4 |
20 |
lower_val |
346252 |
1 |
|
|
T1 |
134 |
|
T2 |
2 |
|
T3 |
394 |
zero_val |
8 |
1 |
|
|
T168 |
2 |
|
T169 |
2 |
|
T170 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45921 |
1 |
|
|
T1 |
10 |
|
T13 |
96 |
|
T14 |
83 |
higher_val |
higher_val |
auto[1] |
40439 |
1 |
|
|
T1 |
27 |
|
T3 |
78 |
|
T4 |
1 |
higher_val |
lower_val |
auto[0] |
46061 |
1 |
|
|
T1 |
22 |
|
T13 |
85 |
|
T14 |
59 |
higher_val |
lower_val |
auto[1] |
39923 |
1 |
|
|
T1 |
23 |
|
T3 |
86 |
|
T4 |
1 |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T169 |
2 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
45698 |
1 |
|
|
T1 |
19 |
|
T13 |
84 |
|
T14 |
65 |
lower_val |
higher_val |
auto[1] |
40178 |
1 |
|
|
T1 |
21 |
|
T3 |
125 |
|
T4 |
6 |
lower_val |
lower_val |
auto[0] |
45863 |
1 |
|
|
T1 |
14 |
|
T13 |
74 |
|
T14 |
57 |
lower_val |
lower_val |
auto[1] |
40212 |
1 |
|
|
T1 |
21 |
|
T3 |
93 |
|
T4 |
7 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T170 |
1 |
|
T171 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T168 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
708 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
193 |
1 |
|
|
T23 |
1 |
|
T24 |
3 |
|
T172 |
1 |
zero_val |
lower_val |
auto[0] |
657 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T4 |
1 |
zero_val |
lower_val |
auto[1] |
230 |
1 |
|
|
T1 |
1 |
|
T23 |
1 |
|
T24 |
3 |