Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339442 |
1 |
|
|
T1 |
125 |
|
T2 |
1 |
|
T3 |
381 |
auto[1] |
3330 |
1 |
|
|
T4 |
4 |
|
T16 |
18 |
|
T18 |
1 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
306125 |
1 |
|
|
T1 |
35 |
|
T2 |
1 |
|
T3 |
381 |
auto[1] |
36647 |
1 |
|
|
T1 |
90 |
|
T4 |
14 |
|
T15 |
81 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329653 |
1 |
|
|
T1 |
123 |
|
T2 |
1 |
|
T3 |
381 |
auto[1] |
13119 |
1 |
|
|
T1 |
2 |
|
T4 |
6 |
|
T15 |
109 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13119 |
1 |
|
|
T1 |
2 |
|
T4 |
6 |
|
T15 |
109 |
sw_kmac_invalid_sideload |
329653 |
1 |
|
|
T1 |
123 |
|
T2 |
1 |
|
T3 |
381 |
app_valid_sideload |
13119 |
1 |
|
|
T1 |
2 |
|
T4 |
6 |
|
T15 |
109 |
app_invalid_sideload |
329653 |
1 |
|
|
T1 |
123 |
|
T2 |
1 |
|
T3 |
381 |