Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100443043	1			T1	1521		T2	575211		T3	109425
all_values[1]	100443043	1			T1	1521		T2	575211		T3	109425
all_values[2]	100443043	1			T1	1521		T2	575211		T3	109425

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

607215

1

T1

105

T2

3

T3

22

auto[1]

300721914

1

T1

4458

T2

172563

T3

328253

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299800437

1

T1

3915

T2

171507

T3

327165

auto[1]

1528692

1

T1

648

T2

10563

T3

1110

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	199033	1			T1	74		T2	1		T3	9
all_values[0]	auto[0]	auto[1]	2079	1			T1	14		T2	2		T3	10
all_values[0]	auto[1]	auto[0]	99734446	1			T1	1231		T2	571689		T3	109046
all_values[0]	auto[1]	auto[1]	507485	1			T1	202		T2	3519		T3	360
all_values[1]	auto[0]	auto[0]	204243	1			T13	1950		T17	9		T19	2
all_values[1]	auto[0]	auto[1]	1554	1			T13	2		T17	7		T19	1
all_values[1]	auto[1]	auto[0]	99729236	1			T1	1305		T2	571690		T3	109055
all_values[1]	auto[1]	auto[1]	508010	1			T1	216		T2	3521		T3	370
all_values[2]	auto[0]	auto[0]	198757	1			T1	15		T3	1		T14	6
all_values[2]	auto[0]	auto[1]	1549	1			T1	2		T3	2		T14	5
all_values[2]	auto[1]	auto[0]	99734722	1			T1	1290		T2	571690		T3	109054
all_values[2]	auto[1]	auto[1]	508015	1			T1	214		T2	3521		T3	368