Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
375196 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
316786 |
1 |
|
|
T1 |
286 |
|
T2 |
4672 |
|
T3 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174177 |
1 |
|
|
T1 |
58 |
|
T2 |
1208 |
|
T3 |
140 |
lower_val |
171573 |
1 |
|
|
T1 |
80 |
|
T2 |
1192 |
|
T3 |
100 |
zero_val |
1809 |
1 |
|
|
T1 |
3 |
|
T2 |
5 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345936 |
1 |
|
|
T1 |
138 |
|
T2 |
2306 |
|
T3 |
256 |
lower_val |
346034 |
1 |
|
|
T1 |
150 |
|
T2 |
2368 |
|
T3 |
236 |
zero_val |
12 |
1 |
|
|
T82 |
2 |
|
T143 |
2 |
|
T144 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[0]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47230 |
1 |
|
|
T13 |
41 |
|
T14 |
586 |
|
T15 |
98 |
higher_val |
higher_val |
auto[1] |
39837 |
1 |
|
|
T1 |
28 |
|
T2 |
602 |
|
T3 |
69 |
higher_val |
lower_val |
auto[0] |
46921 |
1 |
|
|
T13 |
41 |
|
T14 |
559 |
|
T15 |
103 |
higher_val |
lower_val |
auto[1] |
40186 |
1 |
|
|
T1 |
30 |
|
T2 |
606 |
|
T3 |
71 |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T145 |
1 |
|
T146 |
1 |
|
T147 |
1 |
lower_val |
higher_val |
auto[0] |
46878 |
1 |
|
|
T3 |
1 |
|
T13 |
50 |
|
T14 |
561 |
lower_val |
higher_val |
auto[1] |
38864 |
1 |
|
|
T1 |
33 |
|
T2 |
598 |
|
T3 |
54 |
lower_val |
lower_val |
auto[0] |
46411 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
52 |
lower_val |
lower_val |
auto[1] |
39418 |
1 |
|
|
T1 |
46 |
|
T2 |
593 |
|
T3 |
45 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T144 |
1 |
|
T146 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
694 |
1 |
|
|
T3 |
1 |
|
T13 |
2 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
219 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T24 |
3 |
zero_val |
lower_val |
auto[0] |
691 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
205 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
1 |