Group : kmac_env_pkg::kmac_env_cov::error_cg
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Group : kmac_env_pkg::kmac_env_cov::error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
89.66 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 21 3 18 85.71
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cmd 4 0 4 100.00 100 1 1 0
kmac_err_code 9 3 6 66.67 100 1 1 0
mode 3 0 3 100.00 100 1 1 0
strength 5 0 5 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
all_invalid_cmd_in_app_active 1 0 1 100.00 100 1 1 0
all_invalid_mode_strength_cfgs 7 0 7 100.00 100 1 1 0


Summary for Variable cmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[CmdNone] 0 Excluded
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CmdStart] 635 1 T29 28 T30 19 T31 19
auto[CmdProcess] 96 1 T29 7 T30 3 T31 2
auto[CmdManualRun] 320 1 T29 26 T30 8 T31 4
auto[CmdDone] 1336 1 T29 48 T30 31 T31 39



Summary for Variable kmac_err_code

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 9 3 6 66.67


Automatically Generated Bins for kmac_err_code

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[ErrFatalError] 0 1 1
auto[ErrPackerIntegrity] 0 1 1
auto[ErrMsgFifoIntegrity] 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
auto[ErrNone] 0 Excluded
auto[ErrWaitTimerExpired] 0 Illegal
auto[ErrIncorrectEntropyMode] 0 Illegal
auto[ErrSwHashingWithoutEntropyReady] 0 Illegal
auto[ErrShadowRegUpdate] 0 Illegal
il 0 Illegal
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ErrKeyNotValid] 50 1 T20 1 T21 1 T22 1
auto[ErrSwPushedMsgFifo] 42 1 T29 3 T31 1 T32 1
auto[ErrSwIssuedCmdInAppActive] 54 1 T30 2 T31 4 T32 2
auto[ErrUnexpectedModeStrength] 581 1 T29 20 T30 12 T31 16
auto[ErrIncorrectFunctionName] 543 1 T29 25 T30 19 T31 18
auto[ErrSwCmdSequence] 1185 1 T29 61 T30 28 T31 25



Summary for Variable mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[Sha3] 404 1 T29 10 T30 11 T31 5
auto[Shake] 369 1 T29 35 T30 6 T31 8
auto[CShake] 1632 1 T29 64 T30 44 T31 51



Summary for Variable strength

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for strength

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[L128] 835 1 T29 43 T30 20 T31 21
auto[L224] 255 1 T29 10 T30 1 T31 7
auto[L256] 763 1 T20 1 T29 32 T21 1
auto[L384] 284 1 T29 13 T30 14 T31 9
auto[L512] 318 1 T29 11 T30 6 T31 13



Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
invalid_cmds 53 1 T30 2 T31 4 T32 2



Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 7 0 7 100.00


User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sha3_128_cfgs 173 1 T29 4 T30 4 T31 2
shake_224_invalid_cfg 25 1 T29 2 T31 1 T32 2
shake_384_invalid_cfg 28 1 T31 1 T32 1 T152 2
shake_512_invalid_cfg 35 1 T29 1 T30 2 T31 1
cshake_224_invalid_cfg 101 1 T29 2 T30 1 T31 3
cshake_384_invalid_cfg 108 1 T29 7 T30 5 T31 4
cshake_512_invalid_cfg 111 1 T29 4 T31 4 T32 4

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