Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100443043	1			T1	1521		T2	575211		T3	109425
all_pins[1]	100443043	1			T1	1521		T2	575211		T3	109425
all_pins[2]	100443043	1			T1	1521		T2	575211		T3	109425

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300535655	1			T1	4361		T2	172211		T3	327915
values[0x1]	793474	1			T1	202		T2	3519		T3	360
transitions[0x0=>0x1]	791790	1			T1	202		T2	3519		T3	360
transitions[0x1=>0x0]	791814	1			T1	202		T2	3519		T3	360

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99935558	1			T1	1319		T2	571692		T3	109065
all_pins[0]	values[0x1]	507485	1			T1	202		T2	3519		T3	360
all_pins[0]	transitions[0x0=>0x1]	507472	1			T1	202		T2	3519		T3	360
all_pins[0]	transitions[0x1=>0x0]	64	1			T49	7		T156	2		T157	3
all_pins[1]	values[0x0]	100442966	1			T1	1521		T2	575211		T3	109425
all_pins[1]	values[0x1]	77	1			T49	7		T156	2		T157	3
all_pins[1]	transitions[0x0=>0x1]	66	1			T49	7		T156	2		T157	3
all_pins[1]	transitions[0x1=>0x0]	285901	1			T24	897		T29	1437		T25	23745
all_pins[2]	values[0x0]	100157131	1			T1	1521		T2	575211		T3	109425
all_pins[2]	values[0x1]	285912	1			T24	897		T29	1437		T25	23745
all_pins[2]	transitions[0x0=>0x1]	284252	1			T24	890		T29	1437		T25	23589
all_pins[2]	transitions[0x1=>0x0]	505849	1			T1	202		T2	3519		T3	360