Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10526515 |
1 |
|
|
T1 |
5167 |
|
T2 |
27235 |
|
T3 |
3936 |
| auto[1] |
25424114 |
1 |
|
|
T1 |
9708 |
|
T2 |
116850 |
|
T3 |
12300 |
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| word_access |
35832132 |
1 |
|
|
T1 |
14784 |
|
T2 |
143248 |
|
T3 |
16236 |
| triple_byte_access |
39458 |
1 |
|
|
T1 |
32 |
|
T2 |
279 |
|
T13 |
43 |
| halfword_access |
39660 |
1 |
|
|
T1 |
22 |
|
T2 |
279 |
|
T13 |
47 |
| byte_access |
39379 |
1 |
|
|
T1 |
37 |
|
T2 |
279 |
|
T13 |
38 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
word_access |
10408018 |
1 |
|
|
T1 |
5076 |
|
T2 |
26398 |
|
T3 |
3936 |
| auto[0] |
triple_byte_access |
39458 |
1 |
|
|
T1 |
32 |
|
T2 |
279 |
|
T13 |
43 |
| auto[0] |
halfword_access |
39660 |
1 |
|
|
T1 |
22 |
|
T2 |
279 |
|
T13 |
47 |
| auto[0] |
byte_access |
39379 |
1 |
|
|
T1 |
37 |
|
T2 |
279 |
|
T13 |
38 |
| auto[1] |
word_access |
25424114 |
1 |
|
|
T1 |
9708 |
|
T2 |
116850 |
|
T3 |
12300 |