Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101327425	1			T1	112039		T2	222222		T3	111767
all_values[1]	101327425	1			T1	112039		T2	222222		T3	111767
all_values[2]	101327425	1			T1	112039		T2	222222		T3	111767

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

548269

1

T1

15

T2

7

T3

7

auto[1]

303434006

1

T1

336102

T2

666659

T3

335294

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302449464

1

T1

335010

T2

664950

T3

334212

auto[1]

1532811

1

T1

1107

T2

1716

T3

1089

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	187034	1			T1	7		T3	3		T12	1866
all_values[0]	auto[0]	auto[1]	2142	1			T1	8		T3	4		T12	2
all_values[0]	auto[1]	auto[0]	100629454	1			T1	111663		T2	221650		T3	111401
all_values[0]	auto[1]	auto[1]	508795	1			T1	361		T2	572		T3	359
all_values[1]	auto[0]	auto[0]	165550	1			T2	5		T12	4307		T13	192
all_values[1]	auto[0]	auto[1]	1584	1			T2	2		T12	3		T13	1
all_values[1]	auto[1]	auto[0]	100650938	1			T1	111670		T2	221645		T3	111404
all_values[1]	auto[1]	auto[1]	509353	1			T1	369		T2	570		T3	363
all_values[2]	auto[0]	auto[0]	190197	1			T12	1866		T13	192		T14	1
all_values[2]	auto[0]	auto[1]	1762	1			T12	2		T13	1		T14	2
all_values[2]	auto[1]	auto[0]	100626291	1			T1	111670		T2	221650		T3	111404
all_values[2]	auto[1]	auto[1]	509175	1			T1	369		T2	572		T3	363