Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
328528 |
1 |
|
|
T1 |
492 |
|
T2 |
2 |
|
T3 |
492 |
auto[1] |
366210 |
1 |
|
|
T2 |
778 |
|
T12 |
210 |
|
T14 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173833 |
1 |
|
|
T1 |
116 |
|
T2 |
210 |
|
T3 |
141 |
lower_val |
173255 |
1 |
|
|
T1 |
128 |
|
T2 |
227 |
|
T3 |
104 |
zero_val |
1838 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346836 |
1 |
|
|
T1 |
258 |
|
T2 |
416 |
|
T3 |
262 |
lower_val |
347892 |
1 |
|
|
T1 |
234 |
|
T2 |
364 |
|
T3 |
230 |
zero_val |
10 |
1 |
|
|
T144 |
2 |
|
T145 |
2 |
|
T146 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41419 |
1 |
|
|
T1 |
53 |
|
T3 |
77 |
|
T13 |
48 |
higher_val |
higher_val |
auto[1] |
45478 |
1 |
|
|
T2 |
110 |
|
T12 |
19 |
|
T14 |
76 |
higher_val |
lower_val |
auto[0] |
41212 |
1 |
|
|
T1 |
63 |
|
T3 |
64 |
|
T12 |
1 |
higher_val |
lower_val |
auto[1] |
45722 |
1 |
|
|
T2 |
100 |
|
T12 |
16 |
|
T14 |
83 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T144 |
1 |
|
T146 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
40974 |
1 |
|
|
T1 |
68 |
|
T3 |
59 |
|
T13 |
29 |
lower_val |
higher_val |
auto[1] |
45427 |
1 |
|
|
T2 |
124 |
|
T12 |
26 |
|
T14 |
58 |
lower_val |
lower_val |
auto[0] |
40935 |
1 |
|
|
T1 |
60 |
|
T3 |
45 |
|
T13 |
41 |
lower_val |
lower_val |
auto[1] |
45918 |
1 |
|
|
T2 |
103 |
|
T12 |
33 |
|
T14 |
77 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T146 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
680 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
261 |
1 |
|
|
T2 |
2 |
|
T88 |
1 |
|
T31 |
1 |
zero_val |
lower_val |
auto[0] |
645 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T4 |
1 |
zero_val |
lower_val |
auto[1] |
252 |
1 |
|
|
T23 |
2 |
|
T88 |
1 |
|
T31 |
1 |