Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101327425	1			T1	112039		T2	222222		T3	111767
all_pins[1]	101327425	1			T1	112039		T2	222222		T3	111767
all_pins[2]	101327425	1			T1	112039		T2	222222		T3	111767

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	303168848	1			T1	335756		T2	666094		T3	334942
values[0x1]	813427	1			T1	361		T2	572		T3	359
transitions[0x0=>0x1]	811572	1			T1	361		T2	572		T3	359
transitions[0x1=>0x0]	811592	1			T1	361		T2	572		T3	359

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100818630	1			T1	111678		T2	221650		T3	111408
all_pins[0]	values[0x1]	508795	1			T1	361		T2	572		T3	359
all_pins[0]	transitions[0x0=>0x1]	508784	1			T1	361		T2	572		T3	359
all_pins[0]	transitions[0x1=>0x0]	74	1			T22	2		T44	5		T54	2
all_pins[1]	values[0x0]	101327340	1			T1	112039		T2	222222		T3	111767
all_pins[1]	values[0x1]	85	1			T22	2		T44	5		T54	2
all_pins[1]	transitions[0x0=>0x1]	67	1			T22	2		T44	5		T54	2
all_pins[1]	transitions[0x1=>0x0]	304529	1			T22	4910		T23	4114		T28	2080
all_pins[2]	values[0x0]	101022878	1			T1	112039		T2	222222		T3	111767
all_pins[2]	values[0x1]	304547	1			T22	4910		T23	4114		T28	2080
all_pins[2]	transitions[0x0=>0x1]	302721	1			T22	4877		T23	4090		T28	2080
all_pins[2]	transitions[0x1=>0x0]	506989	1			T1	361		T2	572		T3	359