Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	654	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5504	1			T12	20		T13	12		T4	4
len_601_800	12583	1			T12	36		T13	45		T4	6
len_401_600	8282	1			T12	30		T13	22		T4	4
len_201_400	16522	1			T12	4		T13	9		T4	4
len_65_200	73950	1			T12	8		T16	3		T21	2
len_min_for_xof_require_squeeze	1002	1			T44	1		T173	10		T174	1
len_keccak_block_sizes[72]	751	1			T23	2		T173	5		T175	1
len_keccak_block_sizes[104]	750	1			T22	1		T85	2		T23	1
len_keccak_block_sizes[136]	742	1			T176	1		T173	5		T24	1
len_keccak_block_sizes[144]	289	1			T177	1		T173	5		T45	1
len_keccak_block_sizes[168]	287	1			T23	1		T173	5		T178	1
len_datapath_width	14135	1			T1	246		T3	246		T12	1
len_2_63	214531	1			T2	390		T12	2		T13	56
len_1	68	1			T177	1		T179	1		T129	1