Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102167660	1			T1	20335		T2	41595		T3	108348
all_values[1]	102167660	1			T1	20335		T2	41595		T3	108348
all_values[2]	102167660	1			T1	20335		T2	41595		T3	108348

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

597362

1

T2

341

T15

1794

T16

174

auto[1]

305905618

1

T1

61005

T2

124444

T3

325044

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304953114

1

T1

60351

T2

124653

T3

323904

auto[1]

1549866

1

T1

654

T2

132

T3

1140

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	163246	1			T2	339		T16	171		T17	7
all_values[0]	auto[0]	auto[1]	1941	1			T2	2		T16	2		T17	2
all_values[0]	auto[1]	auto[0]	101487792	1			T1	20117		T2	41212		T3	107968
all_values[0]	auto[1]	auto[1]	514681	1			T1	218		T2	42		T3	380
all_values[1]	auto[0]	auto[0]	228014	1			T17	19		T40	3180		T92	2
all_values[1]	auto[0]	auto[1]	1652	1			T17	3		T40	4		T92	1
all_values[1]	auto[1]	auto[0]	101423024	1			T1	20117		T2	41551		T3	107968
all_values[1]	auto[1]	auto[1]	514970	1			T1	218		T2	44		T3	380
all_values[2]	auto[0]	auto[0]	200828	1			T15	1793		T16	1		T18	24
all_values[2]	auto[0]	auto[1]	1681	1			T15	1		T18	2		T40	1
all_values[2]	auto[1]	auto[0]	101450210	1			T1	20117		T2	41551		T3	107968
all_values[2]	auto[1]	auto[1]	514941	1			T1	218		T2	44		T3	380