Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335998 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
368010 |
1 |
|
|
T1 |
292 |
|
T2 |
54 |
|
T3 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176102 |
1 |
|
|
T1 |
91 |
|
T2 |
10 |
|
T3 |
116 |
lower_val |
174005 |
1 |
|
|
T1 |
80 |
|
T2 |
18 |
|
T3 |
133 |
zero_val |
1972 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
351888 |
1 |
|
|
T1 |
144 |
|
T2 |
28 |
|
T3 |
210 |
lower_val |
352116 |
1 |
|
|
T1 |
150 |
|
T2 |
28 |
|
T3 |
282 |
zero_val |
4 |
1 |
|
|
T157 |
2 |
|
T158 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41839 |
1 |
|
|
T1 |
1 |
|
T15 |
52 |
|
T16 |
1 |
higher_val |
higher_val |
auto[1] |
46381 |
1 |
|
|
T1 |
49 |
|
T2 |
3 |
|
T3 |
47 |
higher_val |
lower_val |
auto[0] |
41856 |
1 |
|
|
T15 |
36 |
|
T18 |
30 |
|
T19 |
2 |
higher_val |
lower_val |
auto[1] |
46025 |
1 |
|
|
T1 |
41 |
|
T2 |
7 |
|
T3 |
69 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T157 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
41003 |
1 |
|
|
T15 |
36 |
|
T18 |
36 |
|
T19 |
2 |
lower_val |
higher_val |
auto[1] |
45872 |
1 |
|
|
T1 |
37 |
|
T2 |
10 |
|
T3 |
58 |
lower_val |
lower_val |
auto[0] |
41580 |
1 |
|
|
T15 |
34 |
|
T18 |
26 |
|
T39 |
5 |
lower_val |
lower_val |
auto[1] |
45549 |
1 |
|
|
T1 |
43 |
|
T2 |
8 |
|
T3 |
75 |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T158 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
703 |
1 |
|
|
T1 |
1 |
|
T15 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
303 |
1 |
|
|
T114 |
1 |
|
T120 |
4 |
|
T159 |
3 |
zero_val |
lower_val |
auto[0] |
678 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
1 |
zero_val |
lower_val |
auto[1] |
288 |
1 |
|
|
T114 |
1 |
|
T117 |
2 |
|
T120 |
2 |